The invention relates to a method of testing, using the scan test principle, a circuit which comprises a set of bistable elements and a set of combinatory logic elements connected thereto, for testing a scan chain being formed by a cascade connection of bistable elements which are controlled by the same clock signal, a test cycle comprising the following steps:
an input step during which a stimulus pattern is written into the bistable elements; PA1 a processing step during which a response pattern, formed from the stimulus pattern under the influence of combinatory logic elements, is transferred to the scan chain under the control of the relevant clock signal; PA1 an output step during which the response pattern is serially read from the scan chain.
The invention also relates to a circuit suitable for the use of such a method.
In a circuit comprising a set F of bistable elements, referred to hereinafter as flip-flops, and a set L of combinatory logic elements, where inputs of F (or L) are direct inputs of the circuit or outputs of L (or F) and outputs of F (or L) are direct outputs of the circuit or inputs of L (or F), according to the scan test principle a stimulus pattern is applied, in a test state of the circuit, to the flip-flops which, linked via a test data path so as to form a shift register, constitute one scan chain, and to any direct inputs of the circuit. To this end, the data inputs of the flip-flops may be preceded by multiplexers. The circuit having been set to an execution state, this stimulus pattern is converted in parallel into a response pattern under the influence of the combinatory logic elements, the part of the response pattern which appears on the inputs of the flip-flops being transferred in parallel to the scan chain under the influence of an active portion of the clock signal after which, the circuit having been set to the test state again, said part is serially read, possibly at the same time a next stimulus pattern being serially written into the scan chain. The part of the response pattern which appears on the direct outputs of the circuit can be checked prior to the active portion of the clock signal. The stimulus bits present in the stimulus pattern written into the flip-flops and on the inputs of L unambiguously determine the response bits in the response pattern. Stimulus patterns can be generated, for example by means of an automatic test pattern generator.
The scan test principle is known from U.S. Pat. No. 3,761,695 and is utilized in fully synchronous circuits (circuits which are driven by a single clock signal only). The simultaneous testing of all elements to be scanned is possible only when one clock signal drives the entire circuit.
When use is made of several, non-synchronous clock signals, the following problem is encountered: as soon as a first set of flip-flops which is controlled by a first clock signal stores a response pattern under the influence of an active portion of said first clock signal, these flip-flops no longer supply the correct stimulus bits to the remainder of the circuit; in a second set of flip-flops, controlled by a second clock signal, an incorrect response pattern would then be stored under the influence of a later active portion of said second clock signal.
This problem could be solved by utilizing delay mechanisms for mutually synchronizing the various clock signals. These delay mechanisms, however, often are very difficult to implement in practice and strongly increase the complexity of simulations.